The present invention relates to a thin film transistor (hereafter TFT). In particular it relates to a manufacturing technology for improving the transistor characteristics of the TFT.
The various apparatuses which use TFTs include an active matrix substrate of a liquid crystal display which is formed on a transparent substrate such as a glass plate, and the near central region is designated to be the screen display region 81 as shown in FIG. 12 (A). In this screen display region 81, pixels are formed in blocks by data line 90 and scanning line 91 which are made of metal film, silicide film and conductive semiconductor film of aluminum, tantalum, molybdenum, titanium and tungsten. In each pixel, liquid crystal units 94 (liquid crystal cell) to which image signals are input through TFT 30 for pixel switching are formed. For data line 90, a data side driving circuit 60 with a shift register 84, a label shifter 85, a video line 87, and an analog switch 86 are formed. For the scanning line 91, a scanning side driving circuit 79 with a shift register 88 and the label shifter 89 are formed. In each pixel, a storage capacitor 40 is formed between the scanning line 91 and the capacity line 92 extending parallel to the scanning line 91, which storage capacitor 40 possesses a function to raise maintenance characteristics of the electric charge at the crystal unit 94. Sometimes, the storage capacitor 40 may be formed between the aforementioned scanning line 91 and the pixel electrode.
A CMOS circuit is formed by an N-type TFT 10 and a P-type TFT 20 in the data-side and the scanning-side circuits 60 and 70 as described in FIG. 12 (B). Such CMOS circuit forms an inverter circuit having more than one step in the driving circuits 60 and 70.
Hence, three types of TFT consisting of an N-type TFT 10 for a driving circuit, a P-type TFT 20 for a driving circuit and an N-type TFT 30 for pixel switching on the surface side of the substrate in the active matrix substrate 200. However, the basic structure is common to these TFTs 10, 20 and 30. Hence, to avoid redundancy of description, only the structure and the production method of the N-type TFT for a driving circuit will be described using FIGS. 13, 14, 15 and 16.
On the active matrix substrate 200, a bottom layer protection film 51 made of silicon oxide film is formed on the surface side of the substrate 50, and a polycrystal semiconductor film 100 is formed in island-like pattern on the surface of the bottom layer protection film 51. A gate insulation film 12 is formed on the surface of the semiconductor film 100 and a gate electrode 14 is formed on the surface of the gate insulation film 12. The channel region 15 is formed, through the gate insulation film 12, in the area of the gate electrode 14 towering in the semiconductor film 100. A highly concentrated source region 16 and a highly concentrated drain region 17 are formed on both sides of the channel region 15 being self-aligned with respect to the gate electrode 14. A source electrode 41 and a drain electrode 42 are electrically connected respectively to the highly concentrated source region 16 and the highly concentrated drain region 17 through the contact holes of the inter-layer insulation film 52.
In order to produce the TFT 10 with above structure, first, a substrate 50 made of glass, etc. which is cleansed by super sound wave cleansing is prepared in FIG. 14 (A).
Next, as described in FIG. 14 (B), a bottom layer protection film 51 is formed covering entire surface of the substrate 50 under temperature conditions of about 150xc2x0 C. to 450xc2x0 C. substrate temperature.
Next, as described in FIG. 14 (C), a semiconductor film 100 is formed on the surface of the bottom layer protection film 51, during which time, heat deformation of the glass substrate 50 is prevented by applying a low temperature process. The low temperature process is a process in which the maximum temperature of the process (the maximum temperature to which the entire substrate reaches simultaneously) is below about 600xc2x0 C. (preferably below about 500xc2x0 C.). On the other hand, a high temperature process is a process in which the maximum temperature of the process (the maximum temperature to which the entire substrate reaches simultaneously) is more than about 600xc2x0 C. Film formation under high temperature or heat oxidation of silicon is a high temperature process of 700xc2x0 C. to 1200xc2x0 C.
However, during a low temperature process, formation of polycrystal semiconductor film directly on the substrate is impossible, hence, first non-crystal semiconductor film 100 is formed using a plasma CVD method or low pressure CVD method, and then the semiconductor film 100 is crystallized as described below. The SPC method (Solid Phase Crystallization) or RTF method (Rapid Thermal Annealing) may be considered as a method of crystallization to be used here. However, with the application of laser annealing (ELA: Excimer Laser Annealing/crystallization process) in which XeCl excimer laser beam is irradiated, as described in FIG. 14 (D), a rise in the substrate temperature is prevented and polycrystal Si with large granule diameter is obtained.
In this crystallization process, a laser beam (excimer laser) from the laser beam source 320 is irradiated, through the optical system 325, towards the substrate 50 being mounted on the stage 310 as described in FIG. 15, for example. During this process, the line beam L0 with the irradiation region L being longer in X-direction (for example, the line beam with laser pulse repeat frequency of 200 Hz) is irradiated on the semiconductor film 100, and the irradiation region L is shifted in Y-direction. Here, the beam length of the line beam L0 is 400 mm with an output intensity being 300 mJ/cm2, for example. Moreover, in shifting the irradiation region L of the laser beam, the line beam is scanned in such a manner that the section equivalent to 90% of the peak value of the laser intensity in the width direction overlaps for each region. As a result, non-crystal semiconductor film 100 fuses once and is polycrystallized after a cooling solidification process. During this process, because the irradiation time of the laser beam on each region is very short and because the irradiation region is local compared to the entire substrate, simultaneous heating of the entire substrate 50 with high temperature does not occur. For this reason, heat deformation or cracks are prevented for the glass substrate being used as the substrate 50, though the glass substrate is inferior to the quarzt substrate in heat resistance.
Next, island-like patterning is performed on the polycrystal semiconductor film 100 using a photo lithography technique, as described in FIG. 14(E).
Then, a gate insulation film 12 made of silicon oxide film is formed with respect to the surface side of the semiconductor 100, as described in FIG. 16(A).
Next, a conductive film 140 containing aluminum, tantalum, molybdenum, titanium and tungsten is formed by a sputter method as described in FIG. 16(B).
Then a gate electrode 14 is formed by patterning the conductive film 140, as described in FIG. 16 (D), after forming a resist mask 301 on the surface of the conductive film 140 as described in FIG. 16 (C).
Next, phosphate ions with dosage of about 1015 cmxe2x88x922, for example, are knocked-in with respect to semiconductor film 100 using the gate electrode 14 as a mask. As a result, the highly concentrated source region 16 and drain region 17 with an impurity concentration of about 1020 cmxe2x88x923 are formed on the semiconductor film 100 being self-aligned with respect to the gate electrode 14. The section of the semiconductor film 100 where impurities are not introduced becomes the channel region 15.
Next, annealing is performed for activation after the formation of the inter-layer insulation film 52, as described in FIG. 13. Then, the source electrode 41 and the drain electrode 42 are formed after formation of contact holes in the inter-layer insulation film 52.
In the N-type TFT with aforementioned structure, a positive drain voltage is applied on the drain electrode 42 and a positive gate voltage is applied on the gate electrode 14 for the electric potential of the source electrode 16, as described in FIG. 17 (A). As a result, negative electric charges are concentrated on the interface between the channel region 15 and the gate insulation film 12, and the N-type channel 151 (reverse layer) is formed. If the drain voltage is sufficiently smaller than the gate voltage during this process, due to a connection of the source region 16 to the drain region 17 at the channel 151, the drain current increases rapidly (non-saturation region) with the rise of the drain voltage as shown by real line L0 in the transistor characteristics (current-voltage characteristics) in FIG. 18.
On the other hand, as the drain voltage rises nearly to the gate voltage, the electron density being induced becomes small and pinch-off phenomena occurs in the vicinity of the drain region 17, as described in FIG. 17(B). In this state, even if the drain voltage is further increased, the drain current does not increase but reaches a nearly constant state (saturation region) as described by the real line L0 in FIG. 18. The value of the current at this time is called a saturation current. For this reason, if the TFT 10 is driven using this saturation current, a constant drain current is obtained and the destruction of the TFT 10 itself and the circuit in the vicinity due to excess current may be prevented.
As described above, the transistor characteristics, basically, are controlled only by the behavior of multiple carriers (electrons in the case of the N-type and holes in the case of the P-type). However, if the drain voltage rises, a phenomena occurs in which aforementioned drain current, which is supposed to be constant, rises abnormally high (kink effect), with a possibility of the occurrence of bipolar action in some cases.
Of these phenomena, the kink effect causes the following problems. First, if the drain voltage increases in the TFT and the electric field between source region and drain region becomes stronger, the carriers are accelerated by this electric field and begin to possess large energy. The carriers are accelerated in the direction from the source region 16 to the drain region 17, possessing the maximum energy in the vicinity of the drain region 17. The carriers with large energy (hot carriers) collide with atoms composing the semiconductor film or impure atoms, and generate a pair of an electron and a hole. The hole being generated increases the voltage of the channel region 15 and lowers the threshold voltage, causing an increase in the current between source region and drain region. As a result, in a TFT of the prior art, the drain current increases rapidly with the rise of the drain voltage as described by the broken line in FIG. 18, which may cause destruction of the TFT itself or of circuits in the vicinity. Moreover, such phenomena becomes more frequent with an increase in the level of on-current of the TFT 10 through an increase in the crystallization level of the semiconductor 100, hence in the TFT 10 of the prior art the reliability tends to drop as the on-current level increases.
Moreover, the bipolar action causes the following problem. First, when the barrier between the channel and the source region becomes large with a further increase in the voltage of the channel region 15, the current flows from the channel region 15 to the source region, triggering a flow of an even larger current between the source region and the drain region. Hence, in such phenomena the channel region 15 may be considered as a base, the source region 16 as an emitter and the drain region 17 as a collector respectively. In other words, the current caused by the hole flowing from the channel region 15 to the source region 16 may be considered as base current, while the current flowing between the source region 16 and the drain region 17 may be considered collector current corresponding to the current flowing from the channel region 15 to the source region 16.
In short, the aim of the present invention is to provide a TFT and its production method with stable saturation current and improved reliability by improving the film quality of the channel region.
In order to resolve aforementioned problems, a thin film transistor of the present invention is of the type wherein channel regions which tower through the gate insulation film in the gate electrode and source drain regions connected to said channel regions are formed against a semiconductor film being formed on the surface of an insulation substrate, and recombination centers which capture carriers are formed in said channel regions by part of crystal semiconductor films with relatively low degree of crystallization among crystal semiconductor films forming said channel regions.
In the TFT of the present invention, the channel region 15 towering over the gate electrode 14 through the gate insulation film 12 and the source region 16 and the drain region 17 connecting the channel region 15 are formed from the semiconductor film 100 which is formed on the surface of the insulation substrate 50, and the recombination center 150 which captures small-number carriers using a section with a relatively low degree of crystallization, is formed in the channel region 15, as described in the basic conceptualization of FIG. 17 (D). In such a TFT (an N-type TFT, for example), even if a pair of a hole and an electron is generated by the hot carrier with an increase in drain voltage, the hole and electron are recombined and captured at the recombination center 150 formed in the channel 15. For this reason, the electric potential of the channel region 15 does not increase and the threshold voltage does not drop. Moreover, the hole density of the channel region 15 does not increase as much as placing of holes into the source region 16, hence the placing of the electrons from the source region 16 into the channel region 15 caused by the placing of the holes do not occur. Hence, there is no change in saturation current. For this reason, in the TFT of the present invention the drain current does not increase substantially, even if the drain voltage changes in the saturation region as indicated by the dotted line L2 or the broken line L3 in FIG. 18. As a result, the destruction of the TFT itself and circuits in the vicinity thereof by excess current may be prevented and reliability may be improved.
In the present invention, the recombination center is preferably concentrated in the vicinity of the drain region within the aforementioned channel region. In fact, the recombination center is preferably concentrated in the region whose distance from the drain region is suited to about ⅓ to {fraction (1/10)} of the channel length within said channel region.
In the present invention, the region where said recombination center is concentrated may be formed as a section in which the film thickness is different from other regions among the channel regions.
In the present invention, the region where said recombination center is concentrated may be formed as a section in which the position of the surface height is different from other regions among the channel regions.
In the present invention, in order to form the region where said recombination center is concentrated as a section in which the position of the surface height is different from other regions among the channel regions, a structure in which the thickness of the semiconductor film forming said channel region is made to differ partially may be applied.
Moreover, in forming the region where said recombination center is concentrated as a section in which the position of the surface height is different from other regions among the channel regions, an indentation section or bulged section may be formed beforehand in the lower layer of the semiconductor film forming said channel region.
In the present invention, in the manufacturing method of the thin film transistor with the channel region towering over the gate electrode through the gate insulation film and the source region and the drain region connecting the channel region being formed for the semiconductor film which is formed on the surface of the insulation substrate, a section with a relatively low degree of crystallization is formed in a predetermined region of said semiconductor film by performing laser annealing on said semiconductor film after forming the semiconductor film for forming said channel region.
In the present invention, a section with a relatively low degree of crystallization may be formed in a predetermined region of said semiconductor film by performing laser annealing on said semiconductor film after forming the semiconductor film with partially different film thickness as the semiconductor film for forming said channel region.
In the present invention, a section with a relatively low degree of crystallization may be formed in a predetermined region of said semiconductor film by performing laser annealing on said semiconductor film after forming the semiconductor film with a different surface height as the semiconductor film for forming said channel region.
In the present invention, a method in which the thickness of said semiconductor film may be partially changed may be used in order to form the aforementioned semiconductor film with a different surface height.
In the present invention, an indentation section or a bulged section may be formed beforehand in the lower layer side of said semiconductor film in order to form the aforementioned semiconductor film with a different surface height.